As the dimensions of semiconductor devices, e.g., field effect transistors (FET), continue to decrease, it is increasingly difficult to deal with short channel effects, increased on-currents, current leakage and threshold voltage control. For planar single-gate transistor devices, in addition to the gate controlling the channel, fringe fields from the source, drain or substrate also can affect the channel. These fringe fields can lower the threshold voltage and cause drain-induced barrier lowering, which in turn, increases the leakage current of the transistor. In addition, coupling between the source and channel degrades the sub-threshold current such that the ratio of the drive current when the device in the on-state (Ion), versus the sub-threshold current when the device is in the off-state (Ioff), is lowered.
Multi-gate devices provide improved control of the channel, and thus superior Ion:Ioff ratio relative to planar single-gate transistor structures. Nevertheless, there are challenges to overcome if multi-gate devices are to be used in a broad range of applications in integrated circuits. Typically, for ease of fabrication and uniformity of optimized transistor characteristics, the dimensions of all the multi-gate devices in a circuit are the same. This choice, however, can compromise the performance of multi-gate devices intended for specialized applications, such as for delivering a high drive current (e.g., high Ion), or for operating with a low leakage current (e.g., low Ioff).
Accordingly, what is needed is a multi-gate device and its method of manufacture that address the drawbacks of the prior art devices and methods.